1. Field of the Invention
The present invention relates to a semiconductor memory device such as an SRAM.
2. Description of the Related Art
Recent SRAMs are required to have lower operating voltages and achieve high-speed operation. With this regard, a bit-line stray capacity becomes a large problem. The bit-line stray capacity is determined by memory cells and bit-line material as well as the number of cells per bit line. As a technology for reducing the number of cells per line while keeping the memory capacity, an SRAM circuit having a hierarchical bit-line structure has been proposed (Non-patent Document 1: John Wuu et. al., 2005 IEEE International Solid-State Circuits Conference, pp. 488-489, 618).
The hierarchical bit-line structure requires local bit lines for connecting memory cells with local sense amplifiers as well as global bit lines for connecting the local sense amplifiers with I/O. Therefore, it is required to provide excessive wiring layers, which cause the need for extra mask formation in comparison with the circuit having no hierarchical structure and lead to an increased cost of the entire chip.